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MC33486A Rev 2.0, 12/2005
Dual High-Side Switch for H-Bridge Applications
This 33486A is a self-protected dual 15 m high-side switch that incorporates a dual low-side switch control and protection features. This device is used to replace electromechanical relays and discrete devices in power management applications. It is designed for typical DC-motor control in an H-Bridge configuration. The 33486A can directly interface with a microcontroller for control and diagnostic functions. It is PWM-capable and has a self-adjusting switching speed for minimizing electromagnetic emission. Features * * * * * * * * * * Dual 15 m High-Side Switch with Dual Low-Side Control 10 A Nominal DC Current 8.0 V to 28 V Operating Voltage with Standby Current < 10 A High-Side Overtemperature Protection High-Side and Low-Side Overcurrent Protection Current Recopy to Monitor High-Side Current PWM Capability up to 30 kHz Common Diagnostic Output Overvoltage and Undervoltage Detection Cross-Conduction Management
33486A
DUAL HIGH-SIDE SWITCH
DH SUFFIX 98ASH70702A 20-TERMINAL HSOP
ORDERING INFORMATION
Device MC33486ADH/R2 Temperature Range (TA) -40C to 125C Package 20 HSOP
5.0 V
5.0 V 33486A
VBAT VBAT ST IN1 IN2 WAKE Cur R OUT2 GLS2 OUT1 GLS1
MCU
GND
GND
Figure 1. 33486A Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBAT OUT2
CHANNEL 1
GLS2 CHANNEL 2 Over temperature Charge Pump
Thermal Sensor
IN2 2 Input Trigger IN1 Cur R ST
Switching Speed Adjust OUT1
Undervoltage/ Overvoltage Lockout
Current Recopy
Over current
IN2 WAKE Sleep Mode GND
Driver Overload and Cross-Conduction Management
GLS1
Figure 2. 33486A Simplified Internal Block Diagram
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TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VBAT
GND Cur R IN1 GLS1 OUT1 OUT1 OUT1 OUT1 NC NC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
WAKE ST IN2 GLS2 OUT2 OUT2 OUT2 OUT2 NC NC
VBAT
Figure 3. 33486A Terminal Locations Table 1. TERMINAL DEFINITIONS
Terminal 1 2 3 18 4 17 5-8 9 - 12 13 - 16 19 Terminal Name GND Cur R IN1 IN2 GLS1 GLS2 OUT1 NC OUT2 ST Formal Name Ground Load Current Sense Input Channel 1 Input Channel 2 Gate Low-Side 1 Gate Low-Side 2 Output Channel 1 No Connect Output Channel 2 Status for Both Channels Definition This is the ground terminal of the device. The Current Sense terminal delivers a ratio amount of the sum of the high-side currents. These are the device input terminals that directly control their associated outputs. Each input terminal has an internal active pull-down so that the input terminal will not float if disconnected. Each terminal must be connected to one gate of an external low-side MOSFET. Terminals 5, 6, 7, and 8 are the source of the Output Channel 1 15 m high-side MOSFET1. These terminals are not used. Terminals 13, 14, 15, and 16 are the source of the Output Channel 2 15 m high-side MOSFET2. The status output goes low when a fault mode is detected. It is an open drain with an internal clamp at 6.0 V. An external pull-up resistor connected to VDD (5.0 V) is needed. This logic input enables control of the device. (Wake logic LOW = Sleep Mode, Wake logic HIGH = full operation.) The WAKE terminal has a pulldown resistor. The backside TAB is connected to the power supply of the 33486A.
20
WAKE
Wake
TAB
VBAT
Supply Voltage
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Power Supply Voltage: Continuous / Pulse OUT1, OUT2 to VBAT Voltage: Continuous / Pulse IN1, IN2, WAKE, ST Input DC Voltage: Continuous / Pulse IN1, IN2, WAKE Input Current Output DC Output Current, 1 Channel ON, TA = 85C Output Current: Pulse (2) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Thermal Resistance Junction to Case Junction to Ambient (1) Power Dissipation at TCASE 140C (3) ESD All Terminals Human Body Model (4) Machine Mode (5) Terminal Soldering Temperature Notes 1. 2. 3. 4. 5. 6. Device mounted on dual-side printed circuit board with 70 m copper thickness and 10 cm2 copper heatsink (2.5 cm2 on top side and 7.5 cm2 on down side). See high-side output current shutdown, ILIM. Assuming a 150C maximum junction temperature. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). The maximum peak temperature during the soldering process should not exceed 235C (+5.0C / -0C). The time within 5.0C of actual peak temperature should range from 10 s to 30 s max.
(6) (1)
Symbol VBAT VOUT VIN IIN IOUTDC IOUTP TJ TA TSTG RJC RJA PD VESD1 VESD2 TSOLDER
Value - 0.3 to 40 - 0.3 to 40 - 0.3 to 7.0 5.0 10 Self-Limited - 40 to 150 - 40 to 125 - 65 to 150
Unit V V V mA A A C C C C/W
2.0 25 5.0 W V 2000 200 240 C
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 9.0 V VBAT 16 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TJ = 25C under nominal conditions unless otherwise noted.
Characteristic SUPPLY Nominal Operating Voltage Standby Current VBAT < 13.5 V, WAKE = 0 V, IN1 = IN2 = 0 V Supply Current in Operation Mode No PWM, IN1 or IN2 = 5.0 V, WAKE = 5.0 V Supply Current in Operation Mode PWM = 20 kHz, d = 50% Without Load OUTPUTS High-Side Drain to Source On Resistance IOUT = 5.0 A, VBAT > 10 V, TJ = 25C IOUT = 5.0 A, VBAT > 10 V, TJ = 150C High-Side Body Diode Voltage (OUTn to VBAT) IOUT = -5.0 A, TJ = 150C Low-Side Gate Output Voltage Internally Clamped IN1, IN2, WAKE Input Low Levels Input High Levels Input Hysteresis IN1 and IN2 Terminals Only Logic Input Current VIN = 1.5 V VIN = 3.5 V STATUS Status Voltage IST = 1.0 mA, Output in Fault Status Leakage VST = 5.0 V ISTLK - - 10 VST - - 0.5 A V IIN 1.0 - - - - 50 VIL VIH VHYST 0.2 0.6 1.0 A - 3.5 - - 1.5 - V V V VGS - - 14 VBD - - 0.7 V RDS(ON) - - 12 21 15 30 V m IONPWM - 15 - ION - 9.0 15 mA VBAT ISTDBY - - 10 mA VUV - VOV V A Symbol Min Typ Max Unit
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STATIC ELECTRICAL CHARACTERISTICS
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 9.0 V VBAT 16 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TJ = 25C under nominal conditions unless otherwise noted.
Characteristic OVERLOAD PROTECTION High-Side Output Current Shutdown Low-Side Over Load Detection (VOUT - GND) Thermal Shutdown Thermal Shutdown Hysteresis Undervoltage Shutdown Threshold Undervoltage Shutdown Hysteresis Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis CURRENT RECOPY Current Recopy Ratio IOUT from 4.0 A to 8.0 A, TJ = -40C to 105C IOUT from 2.0 A to 4.0 A, TJ = -40C to 105C CR 3145 2960 3700 3700 4255 4440 - ILIM VOUT - FAULT TSHUT THYST VUV VUYST VOV VOV - HYST 20 1.0 150 - 6.0 - 27 - 35 - 175 10 7.0 0.15 29 0.15 50 1.6 190 - 8.0 - 31 - A V C C V V V V Symbol Min Typ Max Unit
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 9.0 V VBAT 16 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TJ = 25C under nominal conditions unless otherwise noted.
Characteristic OVERLOAD PROTECTION High-Side Overcurrent Shutdown Delay (7) Low-Side Over Load Detection (VOUT - GND) Shutdown Delay (8) OUTPUT TIMING High-/ Low-Speed Mode to Low-/ High-Speed Mode Transition Pulse Width Gate Low-Side Rise Time in High Speed Mode From 10% to 90% VOUT, Load = 3.3 nF and 10 Gate Low-Side Fall Time in High Speed Mode From 90% to 10% VOUT, Load = 3.3 nF and 10 HIGH-SPEED MODE High-Side Positive Slew Rate From 10% to 65% VOUT, Load = 3.0 High-Side Negative Slew Rate From 90% to 35% VOUT, Load = 3.0 High-Side Turn-On Delay Time To 10% VOUT, Load = 3.0 High-Side Turn-Off Delay Time To 90% VOUT, Load = 3.0 LOW-SPEED MODE High-Side Maximum Output Positive Slew Rate From 10% to 65% VOUT, Load = 3.0 High-Side Maximum Output Negative Slew Rate From 90% to 35% VOUT, Load = 3.0 High-Side Turn On Delay TIme To 10% VOUT, Load = 3.0 High-Side Turn Off Delay Time To 90% VOUT, Load = 3.0 Notes 7. Time between fault occurrence and output shutdown. 8. Time between fault occurrence and gate low-side (GLS) shutdown. tLOFF - 80 - tLDON - 10 - s tLF - 0.5 - s tLR - 1.0 - V/s V/s t HDOFF - 1.5 - t HDON - 2.5 - s t HF - 40 - s t HR - 10 - V/s V/s t NSRLS - 0.25 - t SMOD t PSRLS - 3.6 - s 150 250 350 s s t ILIM t OUT-FAULT - - 3.0 3.0 20 10 s s Symbol Min Typ Max Unit
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TIMING DIAGRAMS
TIMING DIAGRAMS
IN In
VBAT Vbat
90% of V 90% of Vbat BAT
40% of VBAT 40% of Vbat tthr A HRA
10% of Vbat 10% of VBAT
60%60% of Vbat of VBAT tthf A HFA
20% of Vbat 20% of VBAT
OUT t HDON thdon t HDOFF thdoff
Figure 4. Outputs Slew Rate and Timing Delay
Out
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The full bridge is partitioned into three blocks, the 33486A and two low-side MOSFETS. Each block has a dedicated package. The 33486A incorporates two 15 m N-channel high-side power MOSFETS and two low-side gate drivers. The outputs are fully protected against shorts to ground, shorts to VBAT, shorted loads, overvoltage / undervoltage, and overtemperature. The device can directly interface with a microcontroller for control and diagnostic functions. The 33486A is designed for typical DC-motor control in an H-Bridge configuration.
FUNCTIONAL TERMINAL DESCRIPTION SUPPLY VOLTAGE (VBAT)
The backside of the 33486A, called the tab, is the power supply of the device. It has undervoltage and overvoltage detection. In addition to its supply function, the tab contributes to the thermal behavior of the device by conducting the heat from the switching MOSFET to the printed circuit board.
WAKE
The WAKE terminal is used to place the device in a sleep mode. When WAKE terminal voltage is a logic LOW state, the device is in sleep mode and its bias current is at a minimum. The device is enabled and fully operational when WAKE terminal voltage is logic HIGH.
INPUTS (IN1 AND IN2)
IN1 and IN2 terminals are input control terminals used to control the outputs (OUT1 and OUT2) and the gates of the low-side power MOSFETs (GLS1 and GLS2). When the input is a logic LOW, the associated output is low (high-side internal MOSFETs OFF and low-side external MOSFETs ON). (Refer to Table 5, TRUTH TABLE, page 21, for more information.) These terminals are 5.0 V CMOS-compatible inputs.
STATUS (ST)
The status terminal indicates when the device is in fault mode. It reports overtemperature and / or overcurrent faults. It goes active low when a fault mode is detected by the device on either one channel or both simultaneously. Its internal structure is an open-drain architecture with an internal clamp at 6.0 V. An external 10 k pull-up resistor connected to VDD (5.0 V) is needed. Refer to Table 5, TRUTH TABLE.
CURRENT SENSE (CUR R)
The Current Sense terminal delivers a ratio amount (1/ 3700) of the sum of the high-side currents that can be used to generate signal ground-referenced output voltages for use by the microcontroller with a 1.0 k pull-down resistor.
OUTPUTS (OUT1 AND OUT2)
OUT1 and OUT2 terminals are the sources of the internal high-side MOSFETs. OUT1 and OUT2 are controlled using the IN1 and IN2 inputs, respectively. These outputs are current limited and thermally protected.
GROUND (GND)
This terminal is the ground of the device.
GATE LOW SIDE (GLS1 AND GLS2)
GLS1 and GLS2 terminals are the gates of the external low-side MOSFETs. These MOSFETs are controlled using IN1 and IN2 inputs. When the input (INn) is logic HIGH, the associated GLS is grounded to turn off the external low-side MOSFET. (Refer to Table 5, TRUTH TABLE for more information.)
FUNCTIONAL INTERNAL BLOCK DESCRIPTION Power Supply
The 33486A can be directly connected to the power supply line. The device has a standby mode (Wake at low logic level) with a ultra-low consumption (10 A max). In operation when inputs are active, the supply current is up to 20 mA. With the high current and fast switching ability of the 33486A, it is recommended that sufficient capacitance (tens of microfarads) be placed between VBAT and GND of the IC. This will help ensure that the power supply stays within the specified limits. The internal charge pump is activated when Wake is at high logic level. It is self-oscillating with a frequency that can
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
vary typically from 1.0 MHz to 7.0 MHz. It starts operating at low frequency.
Self-Adjusting Switching Speed Mode
This feature allows for reduction in EMC and power dissipation depending on the application. The 33486A has two switching speeds (high and low) depending on the input pulse width. The high-speed condition is active when the delay between two consecutive input edges is below 250 s typical. The low-speed mode is active when the delay between two consecutive input edges is above 250 s typical. The 250 s delay corresponds about to a 2.0 kHz frequency with a duty cycle of 50%.
Reverse Battery Protection
During reverse battery the current flows in the body diodes of the power MOSFETs, which are forward biased. Figure 5 shows the specific protection that must be implemented.
33486
C
Vbat VBAT MC33486
External Low-Side Power MOSFETs
Current Recopy
This feature provides a current mirror with the ratio of 1/ 3700 of the sum of the high-side output current. An external resistor must be connected to the Cur R terminal, then tied to a microcontroller A / D input for analog voltage measurement (see Figure 6). This current recopy uses the well-known Wheatstone bridge principle with the Sense, the Power, and the load as the three known resistances.
gnd GND
VBAT
Owing to the internal zener clamp in the gate of the M1 transistor, the Cur R max voltage is typically 11 V. .
Sense Power
Reverse Battery Protection
Figure 5. Reverse Battery Protection Schematic
A reverse battery component might be needed in the GND or in the VBAT terminal of the application (i.e., diode or MOSFET) in order to achieve both reverse battery and negative transient pulses immunity. If a polarized capacitor is used, it can be placed as shown in in Figure 5.
1 I COPY copy
5000 I LOAD load
M1
A
Cur R Cur R
+ -
Loss of Ground Protection
As Figure 5 shows, a loss of ground will not damage the 33486A because the ground terminal of the device is the same as the ground of the low side.
To A/D
M
External External resistor Resistor
R
MC33486 33486A Ground gnd
Overvoltage/Undervoltage Protection
If the battery voltage falls below 7.0 V typical, the outputs are turned low (low-side MOSFETs ON) in a low-speed mode. The 33486A goes back into normal operation mode as soon as VBAT rises above the undervoltage threshold. The undervoltage protection circuitry has hysteresis. The control circuitry also has an overvoltage detection that turns the external low-side MOSFETs ON and protects the load in case VBAT exceeds 29 V typical. The gate drivers will also be clamped to 14 V to protect the external low-side MOSFETs. The low-side MOSFETs remain in the ON state until the overvoltage condition is removed. Undervoltage and overvoltage are not reported on the status output.
Logic Logic Ground gnd
Figure 6. Current Recopy Principle
In case a ground shift occurs between the MCU and the 33486A, the amplifier A (Figure 6, page 10) will adapt its output to keep the same ICOPY. Of course the shift has to keep between 1.0 V.
Overtemperature Protection
The 33486A incorporates overtemperature protection. Overtemperature detection occurs when an internal high-side MOSFET is in the ON state. When an overtemperature condition occurs, both outputs are affected. Both high-side MOSFETs are turned OFF to protect the 33486A from
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
damage (low-side MOSFETs ON). The overtemperature protection circuitry incorporates hysteresis. Overtemperature fault condition is reported on the status output.
As VGS and VDS are measured in respect to the 33486A ground terminal, it is essential that the low-side source is connected to this same ground in order to prevent false overcurrent detection due to ground shifts.
High-Side Overcurrent Protection
The 33486A incorporates a current shutdown threshold of 35 A typical. When this limit is reached due to an overload condition or a short to ground, the faulty output is tri-stated. To clear the fault, the input (INn) line needs to return low, then on the next high transition the output will be enabled. This information is reported on the status output.
Thermal Management
The high-side block is assembled into a power surface mount package. This package offers high thermal performances and high current capabilities. It offers 10 terminals on each package side and one additional connection, which is the package heat sink (called terminal 21). The heatsink acts as the device power VBAT connection. The junction-to-case thermal resistance is 2.0C/W maximum. The junction-to-ambient thermal resistance is dependant on the mounting technology and if an additional heat sink is used. One of the most commonly used mounting technique consists of using the printed circuit board and the copper lines as heatsink. Figure 7 is an example of printed circuit board layout. It has a total of 10 cm2 additional copper on two sides (2.5 cm2 on the top side and 7.5 cm2 on the down side). Bottom-side PCB 8.0 cm2 Top-side PCB 2.0 cm2
Low-Side Block
The low-side block has control circuitry for two external N-channel power MOSFETs. The low-side control circuitry is PWM capable and protects the low-side MOSFETs in case of overcurrent (short to VBAT). This information is reported on the status output. The low-side gate controls are clamped at 14 V maximum to protect the gates of the low-side MOSFETs. Figures 13, page 15, and 14, page 15, depict the characteristics of the low-side block when a current is sourced from the GLS pin or sinked from the GLS pin, respectively. During normal operation, the outputs OUT1 and OUT2 are driven by the high side. The low-side gate driver will only turn on when the voltage (same connection as OUT1 or OUT2) of the internal high sides is less than 2.0 V, which prevents any cross-conduction in the bridge.
33486A
Low-Side Overcurrent Protection
Unlike the high-side overcurrent circuitry, this overcurrent protection does not measure the current; rather, it measures the effect of current on the low-side power MOSFETs through a condition: VGS > 4.3 V and VDS > 1.0 V. When this set of conditions occurs for 3.0 s typical (blanking time), both outputs OUT1 and OUT2 are tri-stated. The full bridge is tristated to prevent the motor running in case of short to VBAT. Once the fault is removed, the input INn of the OUTn that experienced the fault must be reset in order to recover normal mode operation. The 33486A can be used without the external low-side MOSFETs only if the overcurrent protection condition is not reached. If the external low-side power MOSFETs are not used, a 470 pF capacitor in parallel with a 100 k resistor can be connected at the GLSn pin to prevent the activation of the low-side MOSFET overcurrent protection.
Thermal via from top to downside PCB External PCB (4 x 4 cm)
Figure 7. Printed Board Layout Example (not to scale)
With the above layout, thermal resistance junction-toambient of 25C/W can be achieved. This value is split into: *Junction to case (RJC) = 2.0C/W *Case to ambient (RCA) = 23C/W Lower value can be reached with the help of larger and thicker copper metal, higher number of thermal via from top to bottom side PCB, and the use of additional thermal via from the circuit board to the module case.
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Thermal Model
The junction-to-ambient thermal resistance of the circuit mounted on a printed circuit board can be spit into two main parts: junction-to-case and case-to-ambient resistances. Figure 8 shows a simplified steady state model.
Junction Temperature Node (Volts represent Die Surface Temperature) Power (W) (1.0 A = 1.0 W of Power Dissipation) Switch
Any node temperature can easily be calculated knowing the amount of power flowing through the thermal resistances.
Example
1. Numerical Value *Junction-to-case thermal resistance (RJC): 2.0C/W *Power into the switch: Assuming the device is driving 8.0 A at 150C junction temperature (RDS(ON) at 150C is 40 m), the total power dissipation is 0.04 * 8 * 8 = 2.56 W *Case-to-ambient thermal resistance (RCA): 20C/W 2. Results *Junction-to-case delta temperature: 5.0C (2.5 W x 2.0C/W) *Case delta temperature from ambient: 50C (20C/W x 2.5 W) *Actual junction temperature node will be: 50C + 5.0C = 55C above the ambient temperature. Assuming an 85C ambient temperature, the junction temperature is 85C + 55C = 140C.
RJC
Case Temperature Node
RCA (1.0 = 1.0C/W)
Ambient Temperature Node (1.0 V = 1.0C Ambient Temperature)
Figure 8. Simplified Thermal Model (Electrical Equivalent)
The use of this model is similar to the electrical Ohm law (voltage = resistance x current), where: *Voltage represents temperature. *Current represents power dissipated by the device. *Resistance represents thermal resistance. We finally have: Temperature or delta temperature = power dissipation times thermal resistance; that is, C = W x C/W.
The above example takes into account the junction-toambient thermal resistance, assuming that ambient temperature is 85C. In the case where the device plus its printed circuit board are located inside a module, the ambient temperature of the module should be taken into account. Or an additional thermal resistance from inside module to external ambient temperature must be added. The calculation method remains the same. The low-side block is packaged into D2PAK or DPAK package. Junction-to-case thermal resistance is approximately 2/0C/W. The junction-to-ambient thermal resistance follows the same rules as for the high-side block and is in the same range.
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION TYPICAL ELECTRICAL CHARACTERISTICS
Note tHF A is measured from 60% VBAT to 20% VBAT.
45.0 40.0 35.0
t HRA (V/s) Thr (V/s)
30.0 25.0 20.0 15.0 10.0 5.0 0.0 8 8.0 10 12 Vbat ( V) 14 16
0.5 Ohm 25C 0.5 25C 11.0 25C Ohm 25C 22.0 25C Ohm 25C 33.0 25C Ohm 25C
VBAT (V)
Note tHRA is measured from 10% VBAT to 40% VBAT. Figure 9. High-Speed Positive Slew Rate (tHRA) at 25C for Different Loads
160.0 140.0 120.0
t HFA (V/s) Thf (V/s)
100.0 80.0 60.0 40.0 20.0 8 8.0 10 12 14 16
0.5 Ohm at 25C 0.5 25C 1 1.0 at 25C Ohm 25C 2 2.0 at 25C Ohm 25C 3 3.0 at 25C Ohm 25C
VBAT (V) Vbat (V)
Note tHFA is measured from 60% VBAT to 20% VBAT.
Figure 10. High-Speed Negative Slew Rate (tHFA) at 25C for Different Loads
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
Figure 11. Low-Speed Mode, Oscilloscope Format
IN OUT
Figure 12. High-Speed Mode, Oscilloscope Format
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
ISOURCED (mA) Isourced (mA)
30 30 25 25 20 20
15 15 10 10 5.0 5 0 0 0 0 5.0 5 10 10 15 15
Vbat=9V9.0 V 25C VBAT = 25C
VBAT = 12 V 25C Vbat=12V 25C VBAT = 16 V 25C Vbat=16V 25C
VGLS (V) VGLS(V)
Figure 13. Gate Low-Side (GLS) Sourced Current Capability (High-Speed Mode)
70 60 50 40 30 20 10 0 0 5 5.0 10 15
Vbat=9V 25C
VBAT vbat=12V = 9.0 V 25C VBAT = 12 V 25C 25C V = 16 V 25C
ISINKED (mA) Isinked ( mA)
Vbat=16V 25C
20
BAT
VGLS (V) VGLS (V)
Figure 14. Gate Low-Side (GLS) Sinked Current Capability (High-Speed Mode)
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
6.0 6
tPSRLS ( s) Tpsrls(us)
5.0 5 4.0 4 3.0 3 2.0 2 8.0 8
10
12
14
16
18
VBAT (V) Vbat(V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 at 25C.
Figure 15. Gate Low-Side (GLS) Rise Time (High-Speed Mode)
11 11 10 10 9 9.0 8 8.0 7 7.0 6 6.0
8.0 8 10 12
Tpsrls(us)
tPSRLS ( s)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 at 25C.
V b a t (V )
VBAT (V)
13
14
16
18 18
Figure 16. Gate Low-Side (GLS) Rise Time (Low-Speed Mode)
0.3
tNSRLS ( s) Tnsrls(us)
0.28 0.26 0.24 0.22 0.2 8 8.0 10 12 14 16 18
VBAT (V) Vbat(V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 at 25C. Figure 17. Gate Low-Side Fall Time (High-Speed Mode)
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3 3.0
tTnsrls(us) NSRLS ( s)
2.5
2.0 2
1.5
1 1.0 1.0
8 8.0
10
12
14
16
18
VBAT (V) Vbat(V)
Note Curve is obtained with a load at GLS of 3.3 nF and 10 at 25C. Figure 18. Gate Low-Side Fall Time (Low-Speed Mode)
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
FUNCTIONAL CURVES
IN1 In1
In2 IN2
IN2 In2
In1 IN1
Direction1 Direction1 High Impedance High Impedance
Out1 OUT1
Out1 OUT1
Break to Brake Ground to Ground Direction2 Direction2
OUT2 Out2
GLS1 GLS1
Low Low Current shutdown Current Shutdown IIlim LIM
GLS2 GLS2
Ihs1 I
HS1
GLS1 GLS1
St
Figure 19. Normal Operation
ST
Low Low
Figure 21. Overcurrent on High-Side 1
In 2 IN2
IN1 In 1
IN1 In1
OUT1 O u t1
HS1 o f H S 1 Offf
IN2 In2 High Impedance High Impedance
O u t2 OUT2
HS22 o f f H S Off
OUT2 Out2
G LS1 GLS1
L S 1 On LS1 o n
Out1 OUT1
VOUT Vout -Fault -fault
High Impedance High Impedance
GLS2 G LS2
L S On LS12 o n T h e r m a l s h u td o w n Thermal Shutdown T shut T
Vds>2V Vgs>4.3V > 4.3 V VDS > 2.0 V, VGS AtAt least 8.0 s least 8s GLS1 GLS1
HHysteresis y s te r e s is THYST T h yst
Low Low
TTC C HHS1 S1
SHUT
GLS2 GLS2
Low
St ST
LOW Low
St ST
Low
Figure 20. Overtemperature on High-Side 1
Figure 22. Overload on Low-Side 1
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
ELECTRICAL PERFORMANCE
Temperat ure=25C Temperature = 25C
21 19 17 RDS(ON) in m 15 13
4200 4100 4000 3900 3800
Temperat ure=125C Temperature = 125C Temperat ure=-40C Temperature = -40C
CR
0 50 Tem perature (C) 100 150
11 9 7 5 -50
3700 3600 3500 3400 3300 3200 0
2.0 2 4.0 4 6.0 6 8.0 8
10
IOUT) (A) I( A
Figure 23. RDS(ON) versus Temperature for VBAT > 10 V
Figure 25. CR versus IOUT Overtemperature for VBAT = 10 V
Temper at ur = 25C Temperature e =25C Temper at ur = 125C Temperature e =125C Temper at ur = -40C Temperature e =- 40C
Temperature = 25C Temper atur e=25C Temperature = 125C Temper atur e=125C
Temper atur e=-40C Temperature = -40C
4200 4100 4000 3900 3800
4200 4100 4000 3900 3800 3700 3600 3500 3400 3300 3200
0 0 2.0 2 4.0 4 6.0 6
CCr R
3700 3500 3400 3300 3200
Cr
3600
0
2 2.0
4 4.0
6 6.0
8 8.0
10 10
IOUT (A) I(A)
8.0 8
10
IOUT (A) I(A)
Figure 24. CR versus IOUT Overtemperature for VBAT = 12 V
Figure 26. CR versus IOUT Overtemperature for VBAT = 16 V
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
16 14 12 10 8 6 4 2 0 -50
I(A) IOUT (A)
0
50
100
150
200
Temperature (C) Tem perature(C)
Figure 27. Continuous Current versus Temperature with RJA = 27.5C/W Figure 28.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 5. TRUTH TABLE
Standard H-Bridge Conditions Normal Operation IN1 X 0 1 0 1 IN2 X 0 0 1 1 WAKE 0 1 1 1 1 OUT1 Z L H L H OUT Z L L H H GLS1 L H L H L GLS2 L H H L L ST 1 1 1 1 1 Comment Standby Mode Brake to Ground Direction 1 Direction 2 Not Recommended
(9)
Undervoltage Overvoltage Overtemperature High-Side 1 Overtemperature High-Side 2 Overcurrent High-Side 1 Overcurrent High-Side 2 Overcurrent Low-Side 1 Overcurrent Low-Side 2 Legend 0, L = Low level. 1, H = High level. X = Don't care. Z = High impedance.
X X H L 1 X X X
X X L H X 1 X X
1 1 1 1 1 1 1 1
L L L L Z X Z Z
L L L L X Z Z Z
H H H H L X L L
H H H H X L L L
1 1 0 0 0 0 0 0
(10) (10) (11) (11) (12) (12) (13) (13)
Notes 9. In H-Bridge configuration it is not advisable to short the motor to VBAT . If an overvoltage condition occurred in this mode, it would damage the 33486A. The current recirculation in the low-side MOSFET is a preferred solution, with IN1 = 0 and IN2 = 0. 10. Once the overvoltage condition or undervoltage condition is removed, the H-Bridge recovers its normal operation mode. 11. When the thermal shutdown is reached on one of the high-side MOSFETs, both high sides are turned off with the motor tied to ground. When the overtemperature condition is finished, the H-Bridge recovers it previous normal operation mode. 12. The high-side MOSFET HSn that experienced an overcurrent is latched off. The corresponding output OUTn is open. Once the highside overcurrent condition is removed, the input INn must be reset in order to recover the normal operation mode. 13. When a short to VBAT of one of the low-side MOSFETs occurs, both outputs are opened to prevent the motor from running. Once the low-side overcurrent is removed, the input INn of the output that experienced the fault must be reset in order to recover the normal operation mode. Figure 22, Overload on Low-Side 1, page 18, shows an example. If an overload happens in low-side 1, OUT1 and OUT2 are both put in high impedance. IN2 must be reset to recover normal mode.
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
5.0 V
5.0 V
33486A
VBAT
470 F
10 k ST IN1 MCU IN2 WAKE Cur R
VBAT OUT2 GLS2 OUT1 GLS1
GND
1.0 k
GND
Figure 29. 33486A Typical Application Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
For the most current revision of the package, visit www.freescale.com and do a keyword search using the 98A number for the specific device related to the data sheet.
DW SUFFIX 20-TERMINAL HSOP 98ASH70702A ISSUE B
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PACKAGING PACKAGING DIMENSIONS (CONTINUED)
PACKAGING DIMENSIONS (CONTINUED)
DW SUFFIX 20-TERMINAL HSOP 98ASH70702A ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
Revision 2.0
Date 12/2005
Description of Changes Updated to Freescale Format Added Thermal Addendum
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 1.0) DUAL HIGH-SIDE SWITCH FOR H-BRIDGE APPLICATIONS
Introduction
33486A
20-TERMINAL HSOP
This thermal addendum is provided as a supplement to the MC33486 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet.
Packaging and Thermal Considerations
The MC33486A package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively. TJ1 TJ2
=
DH SUFFIX 98ASH70702A 20-TERMINAL HSOP
Note For package dimensions, refer to the 33486A device datasheet.
RJA11 RJA12 RJA21 RJA22
.
P1 P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below.
Standards Table 6. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance RJAmn
(1)(2)
1.0 1.0 0.2 0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane
m = 1, n=1 19 7.0 51 < 0.5
m = 1, n = 2 m = 2, n = 1 18 6.0 50 0
m = 2, n=2 21 10 53 3.0
RJBmn(2)(3) RJAmn(1)(4) RJCmn(5)
Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad. 33486A
20 Terminal HSOP-EP 1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 30. Thermal Land Pattern for Direct Thermal Attachment per JESD51-5
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
A
VBAT
GND Cur R IN1 GLS1 OUT1 OUT1 OUT1 OUT1 NC NC
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
WAKE ST IN2 GLS2 OUT2 OUT2 OUT2 OUT2 NC NC
VBAT
33486A Terminal Connections
20-Terminal HSOP 1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 31. Thermal Test Board Device on Thermal Test Board
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
Table 7.
Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Area A (mm2) 0 300 600
Material:
Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air
Thermal Resistance
m = 1, n=1 51 35 31 11 7.0 7.0
m = 1, n = 2 m = 2, n = 1 50 34 30 10 7.0 6.0
m = 2, n=2 53 38 33 13 10 9.0
Outline:
RJA
Area A: Ambient Conditions:
RJS
0 300 600
RJA is the thermal resistance between die junction and ambient air. RJS is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package (see Figure 31).
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Analog Integrated Circuit Device Data Freescale Semiconductor
ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 1.0)
60 Thermal Resistance [C/W] 50 40 30 20 10 0
x
RJA11 RJA22 RJA12 = RJA21
0
Heat spreading area A [mm]
300
600
Figure 32. Device on Thermal Test Board RJA
100
Thermal Resistance (CW)
10
1
x
RJA11 RJA22 RJA12 = RJA21
0.1 1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
1.00E+04
Time(s)
Figure 33. Transient Thermal Resistance RJA (1.0 W Step Response) Device on Thermal Test Board Area A = 600 (mm2)
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MC33486A Rev 2.0 12/2005

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